Original Post Date: Wednesday, September 25, 2013

Background:

FPGA design typically uses a library of Tiles (Sets of gates and transistors) and a CAD system to physically lay out the actual active devices on an empty portion of substrate. These devices are interconnected by physical (usually copper) traces to route the signals and perform the desired tasks. The design may be totally customized for a single set of functions and may not need any form of programming. Other designs may allow some parts of the device to be electronically re-programmed to allow the device to be calibrated or adjusted for specific purposes.

 

Estimating Best Practice:

In TruePlanning 12.2, FPGA/ASIC are modeled using the Hardware Cost Object to describe the electronics portion with the  firmware portion modeled  through the Software Cost Object.

 

  • Model your electronics at the board level in Hardware Component, and use the Manufacturing Complexity for Electronics calculator.
  • Increase your “Manufacturing Complexity for Electronics” value by 0.25 if you have ASICs included on the board.
  • For newer ASIC technologies, make sure the Engineering Complexity reflects that you are using unfamiliar or state-of-the-art technology (as described in the Engineering Complexity calculator).
  • For FPGAs, include the hardware purchase price as a throughput in the Purchased Good cost object.
  • For both FPGA and ASIC, model your VHDL code in the Software Component model.  (Be sure to set the “Language” input to VHDL, and that the Functional complexity has the right mix, such as Graphical Functions, control functions, logical functions)

 

In addition below are a couple of key Rules of Thumbs

  • Design Repeat is usually around 50% on the software component due to a lot of the same libraries.
  • Weight is usually around 80% Electronics and 20% Structure on the hardware component.
  • Assume usually 1000 or more produced at a time, so production quantity is set.

 

Enhancements in TruePlanning 2014:

As part of continuing cost research and new capability, the TruePlanning 2014 release (slated for Q3/Q4 of 2013) will contain a new catalog of models for ASIC, FPGA, and detailed electronic module modeling .  The new catalog will have inputs aligned more closely with your way of developing firmware.  We would like to arrange an opportunity to demonstrate this new capability and also get your feedback. If there are specific FPGA capabilities UTAS requires, we would like to work with you to include them.

Please let me know if you have any additional questions.