by John Swaren
| August 27, 2015
Original Post Date: June 29, 2015
Regarding the special case where a Module _only_ integrates commodity (thru-put) components that themselves have no modification/development requirements, I would like to share a recent “lessons learned” in implementing our MicroCircuits catalog.
Typically, for actual module development, TruePlanning calculates hours typically as the sum of the cells, modified by the component pins, modified by the area of the module, modified by the layers of the board. This special case scenario is clearly a case where development labor at the module level is limited to placing/connecting various active elements on the board, including connecting elements between different components.
In this situtation, we recommend considering the following for the Module inputs:
Engineering Complexity’s “scope of design effort” may deserve a lower value. Again, clearly the only real development of the module is the placement, layout & connection of the predesigned logic components.
Percent New Design is likewise a significant driver for Module development. Based on our research and experience it is rare that any project is 100% new design. Our foremost expert stated that it would be extremely rare to see any project with higher than 80% new development. In this special case scenario, we’d expect even expect even a lower value.
Development Index may also deserve reduction. Typically, a Module needs to be fully developed with small components. When using large components with most of the logic already developed, the index should be much smaller.
Number of Layers represents the total number of conductive discrete layers either within or on the surface of the module. Typically, this input indicates the number of photomasks being used to construct the module. Just understand that a large # layers has a big impact on development costs.
Also, for Memory components, consider modeling separately from the Module. In this scenario, where components are pre-designed logic, the Number of Pins is the main driver of module “development” (i.e., connection), as opposed to number of active elements. Take care in using Number of Active Cells, which will contribute to a higher-than-necessary design impact at the module level. We are currently evaluating how to properly suppress the impact of devices such as DDR Memory (with high active cell; low logic) that simply do not impact design at the level of the other devices on the board. With that said, please give us your feedback and thoughts!
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